Semiconductor memories generally include a multitude of memory cells arranged in rows and columns Each memory cell is structured for storing digital information in the form of a “1” or a “0” bit. To write (i.e., store) a bit into a memory cell, a binary memory address having portions identifying the cell's row (the “row address”) and column (the “column address”) is provided to addressing circuitry in the semiconductor memory to activate the cell, and the bit is then supplied to the cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the cell is again activated using the cell's memory address, and the bit is then output from the cell.
Manufacturing lines for integrated circuits are inherently imperfect and invariably introduce defects into circuits etched onto a silicon wafer. Integrated circuit memories are among the densest forms of semiconductor structures. Integrated circuit memories may be stand-alone packaged devices, or may be embedded on logic, system on chip (SOC), or processor chips. As memories become larger, the shear amount of circuitry presents an increasing probability that each memory circuit will contain one or more defects. The density and distribution of manufacturing defects across a silicon wafer may cause a high percentage of memory circuits to have defects while the remaining logic portion of the chip is devoid of defects. To address the defective memories and to enhance chip yield, spare memory elements have been added to integrated memory. The spare memory elements are normally in the form of extra rows or columns of memory cells broadly referred to as “redundancy.”
Built-in self-test (BIST) logic has emerged as a technique for testing chips with embedded memories. BIST logic resides on the chip, and provides stimulus to the memory in the form of various test patterns selected to detect known manufacturing defects. The BIST logic may also examine the memory outputs to evaluate whether the circuitry is functioning properly in response to the provided test pattern. For a memory without redundancy, the detection of a failure means that the chip must be discarded. For a memory with redundancy, the redundant elements may be allocated to the defective memory location(s). For memories with multiple dimensions of redundancy, e.g. spare rows and columns, the self-test logic must make a decision whether to allocate a row or a column for each defective cell location in the memory.
Redundancy can be implemented at the time of manufacture via “hard” implementation techniques. These techniques include allocating redundancy and modifying the integrated circuit to enable appropriate connections. This repair process associates the redundant element(s) with the defective memory locations from then on during the life of the chip. Redundancy can also be implemented via “soft” means where a BIST is executed and redundancy is enabled at each power up of the chip. The soft redundancy calculation information is not retained once power is removed from the chip.
During test, if a single cell failure is encountered; either a spare row or a spare column can be used to repair the memory device. A number of algorithms have been described for repairing a memory device.
In a BIST environment, often deployed to verify a system on a chip, it is not practical to store all of the failing locations since a large memory may be required. Indeed, since BIST functions are ancillary to the purpose for which an integrated circuit is designed, very little space is typically allocated. Instead, the BIST logic must make a determination part way through the testing as to which redundant element dimension to use to repair an identified fault. Historically, several BIST solutions have been employed.
One BIST solution is the arbitrary implementation of redundant elements. In this case, the first failure might have a row allocated to replace the memory cell associated with the failed bit, with the next failed bit being replaced by a column of memory cells, and so on. An arbitrary replacement scheme clearly would not lead to an optimal repair since, for example, a row failure might have a column arbitrarily allocated to a failed element in the row, which would fail to repair the entire row. More generally, an arbitrary scheme may fail to repair a chip that is in fact repairable with the existing redundancy. When non-optimal redundancy implementation techniques are utilized, the yield is diminished since chips which are repairable end up not being repaired. Viable redundancy solutions may be missed when applying a limited redundancy calculation algorithm to a memory having a limited number of redundant elements.
Another BIST environment solution is to place a counter on each one of the columns and count the number of cell failures on each. Based on this fault count, a column with more faults than available redundant rows would be selected as a must-fix column for redundancy repair. Then must-fix rows would be identified. These redundancy calculations would be followed up by repairing remaining failures with any available spare columns and spare rows.
Another method allocates spare rows or columns based on the number of faulty cells detected in a row or column of the memory. A row or column with a larger number of faults is ranked higher than a row or column with a lesser number of faults. Spare rows or columns are allocated in accordance with the recorded rank. This method treats each fault as a hard defect and does not identify marginally failing bits or partial column failures in the memory.
U.S. Pat. No. 6,181,614 illustrates and describes a circuit arrangement and method for dynamically repairing a redundant memory array by using a combination of dynamically-determined repair information, generated from a memory test performed on the redundant memory array, along with persistently-stored repair information to repair the redundant memory array. U.S. Patent Application Publication 2005/0083739 describes a system and a method for dynamically repairing a semiconductor memory. The system includes circuitry for dynamically storing memory element remapping information. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides functional fuses. While these circuits, systems, and methods have introduced improvements, they are based on the assumption that detected faults are “hard” or permanent defects in the memory.
For a stand alone memory chip, the whole memory may be tested with all of the failing locations identified by an external tester. Once all of the failing locations are identified, various redundancy solutions are exercised via software simulation means prior to implementing any of the redundancy in hardware. Often, all possible solutions are exercised prior to selecting the redundancy solution to implement. Such a repair algorithm is described in U.S. Pat. No. 6,940,766. The repair algorithm stores an entire defect matrix, which is applied to a repair algorithm until a repair solution is identified or all redundancies are exhausted. However, embedded memories may not be directly or conveniently accessible by an external tester. In addition, the methodology assumes that detected faults are permanent.
Other approaches to the allocation of redundant elements in a BIST environment have been tried. However, they generally suffer from excessive on-chip logic for the redundancy calculation, result in an efficient redundancy implementation determination, or a combination of both.